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posted Feb 1, 2013, 9:40 AM by Andrey Sadovykh   [ updated Feb 1, 2013, 9:41 AM ]
SOFTEAM R&D team has largely contributed to the finalization of the ENOSYS EU FP7 project. ENOSYS  has successfully delivered a set of tools for high-level synthesis of FPGA systems. The tool flow starts from a application specification with UML with MARTE, state charts and action code. This specification passes through design space exploration, optimization and synthesis tools resulting in generation of a high-performance FPGA system. The design flow is validated to drastically reduce design time and improve time-to-market for embedded systems.
Free tool downloads are available at the project web-site