ENOSYS: Model Driven Design Flow for Systems-on-Chip

posted Mar 1, 2011, 6:46 AM by Andrey Sadovykh   [ updated Mar 1, 2011, 7:13 AM ]
Andrey Sadovykh, Etienne Brosse, Vasilios Chouliaras, Suresh Radia, "ENOSYS: Model Driven Design Flow for Systems-on-Chip", in Proc. of HoPES 04 workshop at the European Conference on Modeling - Foundations and Applications (ECMFA 2010), Paris, France, June 2010. (download)

Abstract: Today, SoC vendors realize that critical decisions must be made long before development teams engage in the hardware and software design for new SoC and programmable SoC-based products. It is becoming clear that hardware-software design and verification must form part of a single, unified effort, whereas the methodologies currently available were intended to aid either hardware-only or software-only development. ENOSYS FP7 project intends to provide an integrated model driven design flow for a rapid development of SoC embedded systems a) by the automated generation of SystemC code from the high-level specification; b) by rapidly determining near-optimal solutions for hardware/software partitioning. This article overviews the motivation, addressed challenges, approach and first lessons learnt by the project.

Keywords: MDE, MARTE, SysML, SoC, integrated design flow, co-design, design space exploration, automated partitioning, automated hardware and software synthesis